An Optimized Coefficient Update Processor for High-Throughput Adaptive Equalizers

A processor for the adaptation of the coefficients in high throughput adaptive equalizers will be presented. The accumulation operation fundamental basis of the adaptation process is split into two steps: A fine-grain carry-save accumulation with timesharing factor 2 collects the products of estimated error and input symbols over a blocklength of 16 input symbols and operates at twice the symbol rate; a master accumulator with timesharing factor 32 collects the block-sums from 16 fine-grain accumulators, multiplies them with the adaptation constant and carries out the final vector merging operation, saturation, tap leakage and radix-4 Booth recoding. Three steps to reduce the power consumption of the fine-grain accumulators will be presented and evaluated for a 14-bit-wide accumulator: The suppression of one state of the redundant codes for the value ”1” in the carry save digit alphabet, i.e. 0 1 or 1 0 , reduces the power consumption by 5.5%; The redundancy-reduced digit alphabet can be exploited to reduce the transistor count of the following full adder by one third, resulting in a significant input capacity reduction which increases the maximumand clock frequency by nearly 15% and an additional reduction of power consumption of 2.7%; Finally an optimized sign extension logic reduces the capacitive load of the input sign bits by 70%, eliminates six of the full adders in the sign extension slices and increases the power reduction to 19.2%. The maximum clock frequency of the accumulator could be increased by 18% due to the reduced internal loads.